Typical dynamic memories store data as charges on storage capacitors. Over time the storage capacitors lose charge and eventually the memory loses data. Dynamic memory devices therefore require a refresh operation to maintain the charge on the storage capacitors and thus maintain data. The refresh operation typically involves sensing the charge on the storage capacitor and reinforcing the charge.
In a dynamic memory such as a Dynamic Random Access Memory (DRAM), the refresh operation does not avoid all losses of data. Loss of data may be due to irreparable hardware failures, referred to as hard errors. DRAMs also experience transient loss of data, referred to as soft errors. The number of soft errors experienced per size of memory and over time is referred to as the Soft Error Rate (SER) or Failure In Time (FIT) rate.
The system data integrity and reliability is often measured by the SER. The SER is responsive to a variety of design, manufacture, and application specific issues. The marginal design of hardware may effect the SER by not considering the most common causes of such failures. Similarly, operating conditions may tend to increase the SER. For example, poor regulation or intentional deregulation of power supplies compromises the ability to correctly sense the contents of the DRAM bit cells. Additionally, operation of the DRAM at high temperatures increases leakage of the storage cell affecting the ability of the cells to maintain the stored charge. Another consideration is packaging, where problems relating to radioactivity, as well as other manufacturing and packaging issues effect the SER. Packaging materials that emit alpha particles and/or cosmic radiation are classically studied sources of SER problems in DRAMs.
In general, DRAM design and manufacture balance SER requirements against cost, as reducing SER typically adds additional circuitry, reduces operating speed and increases power dissipation. As the DRAM industry moves to lower voltage operation, the stored charge of the storage cells is reduced, increasing SER. Additionally, advances in semiconductor process technology and economic pressure to reduce cost by increasing circuit density tend to result in reduction of the capacitance of DRAM storage capacitors. Reduced charge (Q=CV) stored in DRAM bit cells results in increased SER because of an inverse exponential relationship between stored charge and SER.
Various methods have been developed to detect and correct soft and hard errors. An Error Detection And Correction unit (EDAC) is used to detect errors in stored data, and if possible, correct errors in the data. EDACs greatly improve data integrity. The operation of one type of EDAC is based on a code word. Data to be stored in the memory is provided to the EDAC. The EDAC then generates check bits based on the data value. The check bits are then combined with the data to form a code word. The code word is then stored in the memory. To check the data, the EDAC reads the code word from the memory and recalculates the check bits based on the data portion of the code word. The recalculated check bits are then compared to the check bits in the code word. If there is a match, the data is correct. If there is a difference and the error is correctable, the EDAC provides the correct data and check bits as an output. If there is a difference and the error is detectable but uncorrectable, the EDAC reports the occurrence of a catastrophic failure.
A variety of EDAC techniques and circuits are available, as are a variety of methods for generating code words and performing bit checks. Some methods are discussed in U.S. Pat. No. 5,598,422, by Longwell, et al., entitled “Digital computer having an error correction code (ECC) system with comparator integrated into re-encoder,” and in Error-Correction Codes, by W. W. Peterson, 2d edition, MIT Press (1972).
The codeword generated by an EDAC is dependent upon the size of the data component and the required level of detectability and correctability of errors. As the number of errors the EDAC is able to detect and the number of errors the EDAC is able to correct increase, the number of check bits, and thus the number of bits in the codeword increases. As the codeword increases so does the complexity of the EDAC. This complexity adds to the circuitry required and also reduces the speed of operation of the EDAC and therefore of the DRAM.
Therefore a need exists for an efficient method to detect and correct errors in a dynamic memory. A need exists for an EDAC apparatus that reduces the SER even as the size of the memory cell shrinks, and over a broad range of considerations, such as manufacturing, packaging, design, and application. Further, a need exists to develop an integrated method of error detection and correction for an embedded DRAM, where the DRAM includes an array of memory tiles. Still further a need exists to increase the capability of error detection and correction without increasing the complexity of the individual EDAC units.